437 lines
12 KiB
C
437 lines
12 KiB
C
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/* PIPE for LC-2K */
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include <assert.h>
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#define NUMMEMORY 65536 /* maximum number of data words in memory */
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#define NUMREGS 8 /* number of machine registers */
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#define MAXLINELENGTH 1000
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#define ADD 0
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#define NAND 1
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#define LW 2
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#define SW 3
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#define BEQ 4
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#define JALR 5 /* JALR will not implemented for Project 3 */
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#define HALT 6
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#define NOOP 7
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#define NOOPINSTRUCTION 0x1c00000
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typedef struct IFIDStruct {
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int instr;
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int pcPlus1;
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} IFIDType;
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typedef struct IDEXStruct {
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int instr;
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int pcPlus1;
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int readRegA;
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int readRegB;
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int offset;
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} IDEXType;
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typedef struct EXMEMStruct {
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int instr;
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int branchTarget;
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int aluResult;
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int readRegB;
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} EXMEMType;
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typedef struct MEMWBStruct {
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int instr;
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int writeData;
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} MEMWBType;
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typedef struct WBENDStruct {
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int instr;
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int writeData;
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} WBENDType;
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typedef struct stateStruct {
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int pc;
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int instrMem[NUMMEMORY];
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int dataMem[NUMMEMORY];
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int reg[NUMREGS];
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int numMemory;
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IFIDType IFID;
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IDEXType IDEX;
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EXMEMType EXMEM;
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MEMWBType MEMWB;
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WBENDType WBEND;
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int cycles; /* number of cycles run so far */
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} stateType;
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void run();
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void printState(stateType*);
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void printInstruction(int);
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int convertNum(int);
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stateType state;
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stateType newState;
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int
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main(int argc, char *argv[])
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{
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char line[MAXLINELENGTH];
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FILE *filePtr;
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int cont, e, step_count;
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if (argc != 2) {
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printf("error: usage: %s <machine-code file>\n", argv[0]);
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exit(1);
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}
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filePtr = fopen(argv[1], "r");
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if (filePtr == NULL) {
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printf("error: can't open file %s\n", argv[1]);
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perror("fopen");
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exit(1);
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}
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state.pc = 0;
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state.cycles = 0;
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memset(state.reg, 0, sizeof(int)*NUMREGS);
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memset(state.dataMem, 0, sizeof(int)*NUMMEMORY);
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memset(state.instrMem, 0, sizeof(int)*NUMMEMORY);
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state.IFID.instr = NOOPINSTRUCTION;
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state.IDEX.instr = NOOPINSTRUCTION;
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state.EXMEM.instr = NOOPINSTRUCTION;
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state.MEMWB.instr = NOOPINSTRUCTION;
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state.WBEND.instr = NOOPINSTRUCTION;
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/* read in the entire machine-code file into memory */
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for (state.numMemory = 0; fgets(line, MAXLINELENGTH, filePtr) != NULL;
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state.numMemory++) {
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if (sscanf(line, "%d", state.dataMem+state.numMemory) != 1) {
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printf("error in reading address %d\n", state.numMemory);
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exit(1);
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}
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state.instrMem[state.numMemory] = state.dataMem[state.numMemory];
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printf("memory[%d]=%d\n", state.numMemory, state.dataMem[state.numMemory]);
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}
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newState = state;
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run();
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return(0);
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}
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int
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convertNum(int num)
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{
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/* convert a 16-bit number into a 32-bit integer */
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if (num & (1 << 15) ) {
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num -= (1 << 16);
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}
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return num;
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}
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void
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printState(stateType *statePtr)
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{
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int i;
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printf("\n@@@\nstate before cycle %d starts\n", statePtr->cycles);
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printf("\tpc %d\n", statePtr->pc);
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printf("\tdata memory:\n");
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for (i=0; i<statePtr->numMemory; i++) {
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printf("\t\tdataMem[ %d ] %d\n", i, statePtr->dataMem[i]);
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}
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printf("\tregisters:\n");
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for (i=0; i<NUMREGS; i++) {
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printf("\t\treg[ %d ] %d\n", i, statePtr->reg[i]);
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}
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printf("\tIFID:\n");
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printf("\t\tinstruction ");
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printInstruction(statePtr->IFID.instr);
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printf("\t\tpcPlus1 %d\n", statePtr->IFID.pcPlus1);
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printf("\tIDEX:\n");
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printf("\t\tinstruction ");
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printInstruction(statePtr->IDEX.instr);
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printf("\t\tpcPlus1 %d\n", statePtr->IDEX.pcPlus1);
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printf("\t\treadRegA %d\n", statePtr->IDEX.readRegA);
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printf("\t\treadRegB %d\n", statePtr->IDEX.readRegB);
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printf("\t\toffset %d\n", statePtr->IDEX.offset);
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printf("\tEXMEM:\n");
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printf("\t\tinstruction ");
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printInstruction(statePtr->EXMEM.instr);
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printf("\t\tbranchTarget %d\n", statePtr->EXMEM.branchTarget);
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printf("\t\taluResult %d\n", statePtr->EXMEM.aluResult);
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printf("\t\treadRegB %d\n", statePtr->EXMEM.readRegB);
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printf("\tMEMWB:\n");
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printf("\t\tinstruction ");
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printInstruction(statePtr->MEMWB.instr);
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printf("\t\twriteData %d\n", statePtr->MEMWB.writeData);
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printf("\tWBEND:\n");
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printf("\t\tinstruction ");
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printInstruction(statePtr->WBEND.instr);
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printf("\t\twriteData %d\n", statePtr->WBEND.writeData);
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}
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int
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field0(int instruction)
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{
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return( (instruction>>19) & 0x7);
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}
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int
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field1(int instruction)
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{
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return( (instruction>>16) & 0x7);
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}
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int
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field2(int instruction)
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{
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return(instruction & 0xFFFF);
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}
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int
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opcode(int instruction)
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{
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return(instruction>>22);
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}
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void
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printInstruction(int instr)
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{
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char opcodeString[10];
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if (opcode(instr) == ADD) {
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strcpy(opcodeString, "add");
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} else if (opcode(instr) == NAND) {
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strcpy(opcodeString, "nand");
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} else if (opcode(instr) == LW) {
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strcpy(opcodeString, "lw");
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} else if (opcode(instr) == SW) {
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strcpy(opcodeString, "sw");
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} else if (opcode(instr) == BEQ) {
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strcpy(opcodeString, "beq");
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} else if (opcode(instr) == JALR) {
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strcpy(opcodeString, "jalr");
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} else if (opcode(instr) == HALT) {
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strcpy(opcodeString, "halt");
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} else if (opcode(instr) == NOOP) {
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strcpy(opcodeString, "noop");
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} else {
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strcpy(opcodeString, "data");
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}
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printf("%s %d %d %d\n", opcodeString, field0(instr), field1(instr),
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field2(instr));
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}
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int memstage_mux(int reg, int hazard_free_value){
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int result;
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result = hazard_free_value;
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assert(((state.EXMEM.instr >> 22) & 7) == SW);
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if (((state.MEMWB.instr >> 22) & 7) == LW){
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if (((state.MEMWB.instr >> 16) & 7) == reg){
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result = state.MEMWB.writeData;
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}
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}
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return result;
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}
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int exstage_mux(int reg, int hazard_free_value){
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int resolved;
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int result;
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resolved = 0;
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result = hazard_free_value;
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switch ((state.EXMEM.instr >> 22) & 7){
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case ADD: case NAND:
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if ((state.EXMEM.instr & 7) == reg){
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resolved = 1;
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result = state.EXMEM.aluResult;
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}
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break;
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case LW:
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if (((state.EXMEM.instr >> 16) & 7) == reg){
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assert((state.IDEX.instr >> 22) & 7 == SW);
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}
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break;
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}
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if (!resolved){
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switch ((state.MEMWB.instr >> 22) & 7){
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case ADD: case NAND:
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if (((state.MEMWB.instr) & 7) == reg){
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resolved = 1;
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result = state.MEMWB.writeData;
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}
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break;
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case LW:
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if (((state.MEMWB.instr >> 16) & 7) == reg){
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resolved = 1;
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result = state.MEMWB.writeData;
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}
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break;
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}
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if (!resolved){
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switch ((state.WBEND.instr >> 22) & 7){
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case ADD: case NAND:
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if (((state.WBEND.instr) & 7) == reg){
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resolved = 1;
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result = state.WBEND.writeData;
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}
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break;
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case LW:
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if (((state.WBEND.instr >> 16) & 7) == reg){
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resolved = 1;
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result = state.WBEND.writeData;
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}
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break;
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}
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}
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}
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return result;
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}
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void run(){
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int EXMuxTop, EXMuxBottom;
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int stalled;
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int lw_write_reg;
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while (1){
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printState(&state);
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/* check for halt */
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if (opcode(state.MEMWB.instr) == HALT) {
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printf("machine halted\n");
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printf("total of %d cycles executed\n", state.cycles);
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exit(0);
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}
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newState = state;
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newState.cycles++;
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stalled = 0;
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if (((state.IDEX.instr >> 22) & 7) == LW){
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lw_write_reg = (state.IDEX.instr >> 16) & 7;
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switch ((state.IFID.instr >> 22) & 7){
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case ADD: case NAND: case BEQ:
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if (((state.IFID.instr >> 19) & 7) == lw_write_reg) stalled = 1;
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if (((state.IFID.instr >> 16) & 7) == lw_write_reg) stalled = 1;
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break;
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case LW: case SW:
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if (((state.IFID.instr >> 19) & 7) == lw_write_reg) stalled = 1;
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break;
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}
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}
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/* --------------------- IF stage --------------------- */
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if (!stalled){
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newState.IFID.instr = state.instrMem[state.pc];
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newState.IFID.pcPlus1 = newState.pc + 1;
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newState.pc += 1;
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}
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else{
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newState.IFID.instr = state.IFID.instr;
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newState.IFID.pcPlus1 = state.IFID.pcPlus1;
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newState.pc = state.pc;
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}
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/* --------------------- ID stage --------------------- */
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if (!stalled){
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newState.IDEX.instr = state.IFID.instr;
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}
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else{
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newState.IDEX.instr = NOOPINSTRUCTION;
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}
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newState.IDEX.pcPlus1 = state.IFID.pcPlus1;
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newState.IDEX.readRegA = state.reg[(state.IFID.instr >> 19) & 7];
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newState.IDEX.readRegB = state.reg[(state.IFID.instr >> 16) & 7];
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newState.IDEX.offset = convertNum(state.IFID.instr & 0xFFFF);
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/* --------------------- EX stage --------------------- */
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newState.EXMEM.instr = state.IDEX.instr;
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newState.EXMEM.branchTarget = state.IDEX.pcPlus1 + state.IDEX.offset;
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if (((state.IDEX.instr >> 22) & 7) == HALT ||
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((state.IDEX.instr >> 22) & 7) == NOOP){
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EXMuxTop = state.IDEX.readRegA;
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}
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else{
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EXMuxTop = exstage_mux((state.IDEX.instr >> 19) & 7, state.IDEX.readRegA);
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}
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if (((state.IDEX.instr >> 22) & 7) == NAND ||
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((state.IDEX.instr >> 22) & 7) == ADD ||
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((state.IDEX.instr >> 22) & 7) == BEQ){
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EXMuxBottom = exstage_mux((state.IDEX.instr >> 16) & 7, state.IDEX.readRegB);
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}
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else{
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EXMuxBottom = state.IDEX.offset;
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}
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if (((state.IDEX.instr >> 22) & 7) == NAND){
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newState.EXMEM.aluResult = ~(EXMuxTop & EXMuxBottom);
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}
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else if (((state.IDEX.instr >> 22) & 7) == BEQ){
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newState.EXMEM.aluResult = (EXMuxTop == EXMuxBottom);
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}
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else{
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newState.EXMEM.aluResult = EXMuxTop + EXMuxBottom;
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}
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|
|
||
|
|
if (((state.IDEX.instr >> 22) & 7) == HALT ||
|
||
|
|
((state.IDEX.instr >> 22) & 7) == NOOP){
|
||
|
|
newState.EXMEM.readRegB = state.IDEX.readRegB;
|
||
|
|
}
|
||
|
|
else{
|
||
|
|
newState.EXMEM.readRegB = exstage_mux((state.IDEX.instr >> 16) & 7, state.IDEX.readRegB);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* --------------------- MEM stage --------------------- */
|
||
|
|
newState.MEMWB.instr = state.EXMEM.instr;
|
||
|
|
if (((state.EXMEM.instr >> 22) & 7) == LW ||
|
||
|
|
((state.EXMEM.instr >> 22) & 7) == SW){
|
||
|
|
newState.MEMWB.writeData = state.dataMem[state.EXMEM.aluResult];
|
||
|
|
}
|
||
|
|
else{
|
||
|
|
newState.MEMWB.writeData = state.EXMEM.aluResult;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (((state.EXMEM.instr >> 22) & 7) == SW){
|
||
|
|
newState.dataMem[state.EXMEM.aluResult] = memstage_mux((state.IDEX.instr >> 16) & 7, state.EXMEM.readRegB);
|
||
|
|
}
|
||
|
|
|
||
|
|
if (((state.EXMEM.instr >> 22) & 7) == BEQ){
|
||
|
|
if (state.EXMEM.aluResult){
|
||
|
|
newState.pc = state.EXMEM.branchTarget;
|
||
|
|
newState.EXMEM.instr = NOOPINSTRUCTION;
|
||
|
|
newState.IDEX.instr = NOOPINSTRUCTION;
|
||
|
|
newState.IFID.instr = NOOPINSTRUCTION;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/* --------------------- WB stage --------------------- */
|
||
|
|
newState.WBEND.instr = state.MEMWB.instr;
|
||
|
|
newState.WBEND.writeData = state.MEMWB.writeData;
|
||
|
|
|
||
|
|
switch ((state.MEMWB.instr >> 22) & 7){
|
||
|
|
case ADD: newState.reg[(state.MEMWB.instr & 7)] = state.MEMWB.writeData; break;
|
||
|
|
case NAND: newState.reg[(state.MEMWB.instr & 7)] = state.MEMWB.writeData; break;
|
||
|
|
case LW: newState.reg[((state.MEMWB.instr >> 16) & 7)] = state.MEMWB.writeData; break;
|
||
|
|
}
|
||
|
|
|
||
|
|
state = newState; /* this is the last statement before end of the loop.
|
||
|
|
It marks the end of the cycle and updates the
|
||
|
|
current state with the values calculated in this
|
||
|
|
cycle */
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
|