321 lines
7.3 KiB
C
321 lines
7.3 KiB
C
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/* FSM for LC */
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#define NUMMEMORY 65536 /* maximum number of words in memory */
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#define NUMREGS 8 /* number of machine registers */
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#define MAXLINELENGTH 1000
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typedef struct stateStruct {
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int pc;
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int mem[NUMMEMORY];
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int reg[NUMREGS];
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int memoryAddress;
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int memoryData;
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int instrReg;
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int aluOperand;
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int aluResult;
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int numMemory;
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} stateType;
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void printState(stateType *, char *);
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void run(stateType);
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int memoryAccess(stateType *, int);
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int convertNum(int);
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int
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main(int argc, char *argv[])
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{
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int i;
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char line[MAXLINELENGTH];
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stateType state;
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FILE *filePtr;
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if (argc != 2) {
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printf("error: usage: %s <machine-code file>\n", argv[0]);
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exit(1);
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}
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/* initialize memories and registers */
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for (i=0; i<NUMMEMORY; i++) {
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state.mem[i] = 0;
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}
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for (i=0; i<NUMREGS; i++) {
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state.reg[i] = 0;
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}
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state.pc=0;
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/*
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* read machine-code file into instruction/data memory
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* (starting at address 0)
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*/
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filePtr = fopen(argv[1], "r");
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if (filePtr == NULL) {
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printf("error: can't open file %s\n", argv[1]);
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perror("fopen");
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exit(1);
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}
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for (state.numMemory=0; fgets(line, MAXLINELENGTH, filePtr) != NULL;
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state.numMemory++) {
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if (sscanf(line, "%d", state.mem+state.numMemory) != 1) {
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printf("error in reading address %d\n", state.numMemory);
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exit(1);
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}
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printf("memory[%d]=%d\n", state.numMemory, state.mem[state.numMemory]);
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}
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printf("\n");
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/* run never returns */
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run(state);
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return 0;
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}
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void
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printState_(stateType *statePtr, char *stateName, int showAll)
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{
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int i;
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static int cycle = 0;
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printf("\n@@@\nstate %s (cycle %d)\n", stateName, cycle++);
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if (showAll){
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printf("\tpc %d\n", statePtr->pc);
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printf("\tmemory:\n");
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for (i=0; i<statePtr->numMemory; i++) {
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printf("\t\tmem[ %d ] %d\n", i, statePtr->mem[i]);
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}
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printf("\tregisters:\n");
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for (i=0; i<NUMREGS; i++) {
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printf("\t\treg[ %d ] %d\n", i, statePtr->reg[i]);
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}
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printf("\tinternal registers:\n");
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printf("\t\tmemoryAddress %d\n", statePtr->memoryAddress);
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printf("\t\tmemoryData %d\n", statePtr->memoryData);
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printf("\t\tinstrReg %d\n", statePtr->instrReg);
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printf("\t\taluOperand %d\n", statePtr->aluOperand);
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printf("\t\taluResult %d\n", statePtr->aluResult);
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}
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}
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#define printState(s,n) printState_(s,n,1)
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void
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printStateReal(stateType *statePtr, char *stateName)
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{
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printState_(statePtr, stateName, 1);
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}
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/*
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* Access memory:
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* readFlag=1 ==> read from memory
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* readFlag=0 ==> write to memory
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* Return 1 if the memory operation was successful, otherwise return 0
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*/
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int
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memoryAccess(stateType *statePtr, int readFlag)
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{
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static int lastAddress = -1;
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static int lastReadFlag = 0;
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static int lastData = 0;
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static int delay = 0;
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if (statePtr->memoryAddress < 0 || statePtr->memoryAddress >= NUMMEMORY) {
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printf("memory address out of range\n");
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exit(1);
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}
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/*
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* If this is a new access, reset the delay clock.
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*/
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if ( (statePtr->memoryAddress != lastAddress) ||
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(readFlag != lastReadFlag) ||
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(readFlag == 0 && lastData != statePtr->memoryData) ) {
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delay = statePtr->memoryAddress % 3;
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lastAddress = statePtr->memoryAddress;
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lastReadFlag = readFlag;
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lastData = statePtr->memoryData;
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}
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if (delay == 0) {
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/* memory is ready */
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if (readFlag) {
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statePtr->memoryData = statePtr->mem[statePtr->memoryAddress];
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} else {
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statePtr->mem[statePtr->memoryAddress] = statePtr->memoryData;
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}
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return 1;
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} else {
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/* memory is not ready */
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delay--;
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return 0;
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}
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}
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int
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convertNum(int num)
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{
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/* convert a 16-bit number into a 32-bit integer */
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if (num & (1 << 15) ) {
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num -= (1 << 16);
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}
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return num;
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}
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#define OP_ADD 0
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#define OP_NAND 1
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#define OP_LW 2
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#define OP_SW 3
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#define OP_BEQ 4
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#define OP_JALR 5
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#define OP_HALT 6
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#define OP_NOOP 7
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void
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run(stateType state)
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{
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int bus;
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fetch:
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printState(&state, "fetch");
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bus = state.pc;
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state.memoryAddress = bus;
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state.pc++;
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goto fetch2;
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fetch2:
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printState(&state, "fetch2");
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if (memoryAccess(&state, 1)) goto decode1;
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goto fetch2;
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decode1:
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printState(&state, "decode1");
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bus = state.memoryData;
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state.instrReg = bus;
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goto decode2;
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decode2:
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printState(&state, "decode2");
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bus = state.reg[(state.instrReg >> 19) & 7];
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state.aluOperand = bus;
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if ((state.instrReg>>22) == OP_ADD) goto add1;
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if ((state.instrReg>>22) == OP_NAND) goto nand1;
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if ((state.instrReg>>22) == OP_LW) goto lw1;
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if ((state.instrReg>>22) == OP_SW) goto sw1;
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if ((state.instrReg>>22) == OP_BEQ) goto beq1;
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if ((state.instrReg>>22) == OP_JALR) goto jalr1;
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if ((state.instrReg>>22) == OP_HALT) goto halt;
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if ((state.instrReg>>22) == OP_NOOP) goto fetch;
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exit(1);
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add1:
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printState(&state, "add1");
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bus = state.reg[(state.instrReg >> 16) & 7];
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state.aluResult = state.aluOperand + bus;
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goto alu_finish;
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nand1:
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printState(&state, "nand1");
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bus = state.reg[(state.instrReg >> 16) & 7];
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state.aluResult = ~(state.aluOperand & bus);
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goto alu_finish;
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alu_finish:
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printState(&state, "alu_finish");
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bus = state.aluResult;
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state.reg[(state.instrReg) & 7] = bus;
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goto fetch;
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lw1:
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printState(&state, "lw1");
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bus = convertNum(state.instrReg & 0xFFFF);
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state.aluResult = state.aluOperand + bus;
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goto lw2;
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lw2:
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printState(&state, "lw2");
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bus = state.aluResult;
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state.memoryAddress = bus;
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goto lw3;
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lw3:
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printState(&state, "lw3");
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if (memoryAccess(&state, 1)) goto lw4;
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goto lw3;
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lw4:
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printState(&state, "lw4");
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bus = state.memoryData;
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state.reg[(state.instrReg >> 16) & 7] = bus;
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goto fetch;
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sw1:
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printState(&state, "sw1");
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bus = convertNum(state.instrReg & 0xFFFF);
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state.aluResult = state.aluOperand + bus;
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goto sw2;
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sw2:
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printState(&state, "sw2");
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bus = state.aluResult;
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state.memoryAddress = bus;
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goto sw3;
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sw3:
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printState(&state, "sw3");
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bus = state.reg[(state.instrReg >> 16) & 7];
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state.memoryData = bus;
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goto sw4;
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sw4:
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printState(&state, "sw4");
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if (memoryAccess(&state, 0)) goto fetch;
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goto sw4;
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beq1:
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printState(&state, "beq1");
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bus = state.reg[(state.instrReg >> 16) & 7];
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state.aluResult = state.aluOperand - bus;
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goto beq2;
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beq2:
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printState(&state, "beq2");
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bus = convertNum(state.instrReg & 0xFFFF);
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state.aluOperand = bus;
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if (state.aluResult == 0) goto beq3;
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goto fetch;
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beq3:
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printState(&state, "beq3");
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bus = state.pc;
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state.aluResult = state.aluOperand + bus;
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goto beq4;
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beq4:
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printState(&state, "beq4");
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bus = state.aluResult;
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state.pc = bus;
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goto fetch;
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jalr1:
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printState(&state, "jalr1");
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bus = state.pc;
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state.reg[(state.instrReg >> 16) & 7] = bus;
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goto jalr2;
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jalr2:
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printState(&state, "jalr2");
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bus = state.reg[(state.instrReg >> 19) & 7];
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state.pc = bus;
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goto fetch;
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halt:
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printStateReal(&state, "halt");
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exit(0);
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}
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